Muhammad Ali Akhtar
Portland Oregon

I am international Graduate student, at ECE Department Portland State University, Portland Oregon. I am interested in entry level ASIC / FPGA Design Engineer jobs at start up companies in silicon valley. I will be graduating in December 2009 and my OPT application has already been approved. My Resume is attached.

I have more than 1 year of work experience in Hardware design using Xilinx FPGAs. I have done extensive RTL coding in Both Verilog and VHDL. I also have some experience in PCB design using Orcad Schematic Capture. I have successfully completed individual as well as group projects and have been involved in entire product cycle i.e. from Design Specification to final test and bring up of the board.

For ASICs, I have some academic experience in Cadence Virtuoso, Spectre Simulation, SoC Encounter, Mentor Graphics Calibre DesignRev, Calibre DRC,LVS, PEX and ModelSim for simulation.

At Portland State University, I did a research project for the separation for Systematic and Random Yield Loss from the fail diagnosis Data of 90nm ASIC. This project was sponsored by LSI Corporation and Mentor Graphics, which provided the required Diagnosis Data.

For further information, you can reach me at (503) 724-5241 or at muhammadali201@gmail.com

Muhammad Ali Akhtar

Portland, Oregon